Analog front ends of digital signal processors (DSPs), for instance in serial link receivers, commonly include equalizers to compensate for frequency-dependent amplitude and phase effects on the signal caused by the transmission channel.
FIG. 1 shows a schematic of a signal processing device which may be employed for analog baseband equalization. The device comprises an equalizer system 1 comprising a decision feedback equalizer (DFE). The DFE comprises a decision device in the form of a comparator 3 and a feedback path 4 including a delay line with a number N of taps with coefficients h1, h2, . . . hN, where h1 represents the first tap coefficient. Through the feedback path the DFE may cancel postcursor inter-symbol-interference (ISI), at the input of the comparator 3. The sources of the ISI may be various and may depending on the type of context. For instance, ISI may be due to multi-path propagations (e.g. of mmWave wireless channels), bandwidth-limited low-pass channels (either optical or wireline) and/or ISI induced by preceding front-ends.
In view of the ever increasing data rates handled in signal processing devices, it is becoming increasingly important to design equalizers for speed and decision robustness. One notable element of the DFE-based equalizer system is the decision device, i.e. the comparator 3 shown in FIG. 1. Two types of comparators commonly used in high speed applications are dynamic comparators and static comparators. Dynamic comparators offer an advantage of no static power consumption and no hysteresis, due to a reset phase after the comparison. However, dynamic comparators also have disadvantages such as high kick-back noise and high sensitivity to process, supply voltage and temperature (PVT) variations. On the other hand, static comparators may be realized with a comparably small number of transistors, allows high-speed decisions, provides inductive peaking possibilities, do not suffer from kick-back noise issues and are comparably robust against PVT variations.